1. Field of the Invention
The present invention generally relates to a closed-loop system for dynamically distributing memory bandwidth. More specifically, the present invention relates to a closed-loop system for dynamically distributing memory bandwidth between real-time components and non-real-time components based on a measured progress of the real-time components.
2. Background Art
In providing content such as video and audio data in a digital format, digital signals are often transmitted to a Set-Top Box (STB). Typical applications in which a STB is utilized include digital cable television and satellite television. In general, set-top boxes include highly integrated chips developed using System-on-a-Chip (SOC) methodology. The components of the SOC rely on a unified memory architecture to provide the most cost effective memory subsystem. Such an architecture, however, leads to a mixture of functional components that have real-time requirements and functional components that have non-real-time requirements. With such a mixture, the memory allocation between the real-time components and the non-real-time components must be carefully balanced to ensure the functionality thereof is satisfied.
Heretofore, the functionality of the components has been satisfied using an open-loop architecture that provides sufficient excess performance such that all real-time demands are met. This approach has been generally acceptable for low performance components, which may have sufficient memory subsystem performance for the real-time components and very few demands placed on non-real-time components. Unfortunately, for higher functionality components, the open-loop architecture leads to higher cost and/or components of the chip not receiving as much memory allocation as is needed.
In addition, as more demands are placed on the components of a SOC, it as advantageous to maximize the efficiency of the memory subsystem wherever possible. As such, the memory controller may take into account access patterns in its selection of operations to perform. By increasing the efficiency of the memory subsystem, more total work is done by the system for a given memory technology, bus frequency and width. If the entire system has non-real-time demands, then the functional components and memory subsystem could be run entirely open-loop. However, in the case of a STB having real-time components such as video display and decoding, specific deadlines would be missed. Missed deadlines result in unpleasant artifacts such as repeated pictures, audio pops, or visual streaks. Such artifacts are undesirable and may render the STB noncompetitive.
One alternative to open-loop components is to raise the priorities of the real-time components over the non-real-time components so that all real-time deadlines are met. Unfortunately, this wastes bandwidth and thus, useful work since the memory subsystem may not be as efficient since it must be “reserved” for the real-time components. Another alternative is to use a higher frequency or wider memory components to deliver excess bandwidth. As is well known, however, excess memory bandwidth is accompanied with higher costs, which can render the STB noncompetitive in the marketplace. In addition, many existing systems have priority controls that are hard coded or statically defined based on a-priori assumptions on workload. The priority input is generally based on a very fine scale such as the individual bus command or over several commands. Accordingly, no “global” dynamic analysis is performed.
In view of the foregoing, there exists a need for a closed-loop system for dynamically distributing memory bandwidth between real-time components and non-real-time components. A further need exists for a system in which a performance of the real-time components is measured. In addition, a need exists for closed-loop feedback to be provided to a unified memory system so that the memory bandwidth can be distributed with optimal efficiency.